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SPT5230
10-BIT, 36 MWPS TRIPLE VIDEO DAC
FEATURES
* * * * * * 10-Bit Triple Video Digital-to-Analog Converter Output Full-Scale Voltage 0.5 to 2.0 Vp-p 36 MWPS Operation (typ) Low Power: 280 mW (1 Vp-p Output) 5 V Monolithic CMOS 52-pin QFP Package (10mm x 10mm, 0.65 mm pitch)
APPLICATIONS
* * * * * Desktop Video Processing CCIR-601 Video Signal Processing RGB Color Monitors Image Processing Direct Digital Synthesis
GENERAL DESCRIPTION
The SPT5230 is a 10-bit, 36 MWPS triple video digital-toanalog converter specifically designed for high performance, high resolution color graphics monitor applications and video processing applications. A single external resistor controls the full-scale output current. The differential linearity errors of the DACs are guaranteed to be a maximum of 1.0 LSB over the full temperature range. The device is available in a 52lead QFP package over the commercial temperature range.
BLOCK DIAGRAM
ROUT AVDD AVDD IOR AVDD IOG GOUT AVDD BOUT
IOB
VSSA
VREF1
VREF
VREF2 VCS2 VCS1
VCS
Current Switch Cell Array (Cell 4)
Current Switch Cell Array (Cell 255)
Current Switch Cell Array (Cell 4)
Current Switch Cell Array (Cell 255)
Current Switch Cell Array (Cell 4)
Current Switch Cell Array (Cell 255)
Latch
Latch
Latch
Decoder
Decoder
Decoder
Latch
Latch
Latch
(MSB) DG9 DG8 DG7 DG6 DG5 DG4 DG3 DG2 DG1 (LSB) DGO
(MSB) DR9 DR8 DR7 DR6 DR5 DR4 DR3 DR2 DR1 (LSB) DRO
(MSB) DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 (LSB) DBO
CLKG
CLKR
CLKB
ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1
Supply Voltages AVDD (measured to AVSS) ........................... -0.3 to 7.0 V Input Voltage Clock and Data ......................................... AVSS to AVDD Output Current IOUT ........................................................................... 0 to 14 mA Temperature Operating, ambient ........................................ 0 to +70 C Storage ................................................... -55 to + 125 C
Note: 1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal applied conditions in typical applications.
ELECTRICAL SPECIFICATIONS
fCLK = 27 MWPS, AVDD = 5.0 V, Output Pull-Up Load = 75 , TA = 25 C, AVSS = 0.0 V
PARAMETERS DC Performance Resolution Differential Linearity Integral Linearity Analog Outputs Output Voltage Range Conversion Rate Output Offset Voltage Signal-to-Noise Ratio Settling Time1 Propagation Delay (tpd) Crosstalk FS Control Voltage (VCS2) Digital Inputs and Timing Input Current, Logic High Logic Low Set-Up Time, Data and Controls (tS) Hold Time, Data and Controls (th) Clock Duty Cycle Power Supply Requirements Supply Voltage Supply Current Power Dissipation
TEST CONDITIONS
TEST LEVEL
MIN
TYP 10.0
MAX
UNITS Bits LSB LSB V MWPS mV dB ns ns dB V A A ns ns % V mA mA mW mW
TA = TMIN to TMAX
I I I I I I I V I V I I I I V I IV I IV I
-1.0 -2.5 3.0 27 46
1.0 2.0 5.0 36 2.4 52 16 10 -54 14 23 12 4.0 5
VCS2 = +2.1 V
-49 2.0
VIH = 5 V VIL = 0 V
-5 5 10 40 4.75
60 5.25 56 100 280 500
1 Vp-p Output 2 Vp-p Output 1 Vp-p Output 2 Vp-p Output
485
1Full-scale settling time to within 2% of full scale.
TEST LEVEL CODES All electrical characteristics are subject to the following conditions: All parameters having min/max specifications are guaranteed. The Test Level column indicates the specific device testing actually performed during production and Quality Assurance inspection. Any blank section in the data column indicates that the specification is not tested at the specified condition.
TEST LEVEL I II III IV V VI
TEST PROCEDURE 100% production tested at the specified temperature. 100% production tested at TA=25 C, and sample tested at the specified temperatures. QA sample tested only at the specified temperatures. Parameter is guaranteed (but not tested) by design and characterization data. Parameter is a typical value for information purposes only. 100% production tested at TA = 25 C. Parameter is guaranteed over specified temperature range.
SPT5230
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INTERFACE CONSIDERATIONS
Figure 4 shows a typical interface circuit of the SPT5230 in normal circuit operation. SUPPLY AND GROUND CONSIDERATIONS Fairchild suggests that all power supply pins (AVDD) be tied together and decoupled using a 0.1 F ceramic capacitor in parallel with a 10 F tantalum capacitor. EXTERNAL REFERENCE VOLTAGE (VREF1) A +3 V (10%) voltage reference should be externally generated for the VREF1 pin using the simple voltage divider shown in figure 4. Connect a 0.1 F bypass capacitor between VREF1 and AVSS as close to the pin as possible. EXTERNAL REFERENCE VOLTAGE (VREF2) VREF2 needs to be externally connected to AVDD through a 1.2 k (5%) resistor. Connect a 0.1 F bypass capacitor between VREF2 and AVSS as close to the pin as possible. CONTROL VOLTAGE DECOUPLING (VCS1) This is a decoupling pin for the control voltage internal circuitry. An external 0.1 F capacitor should be connected between VCS1 and AVSS as close to the pin as possible. FULL-SCALE ADJUST CONTROL (VCS2) VCS2 is an external control voltage input that controls the peak-to-peak full scale output voltage. This is the only external voltage that has direct control over the SPT5230 output voltage. The voltage output swings between AVDD (+5 V) and a value controlled by VCS2. Assuming that an output load resistor of 75 is connected between the output and AVDD, figure 2 shows what the output voltage will be for the digital inputs all equal to logic 0, as VCS2 is varied from 2 V to 4 V. Figure 3 shows the peak-to-peak output voltage versus VCS2 and table I shows an example in which VCS2 is equal to 2.1 V.
CURRENT OUTPUTS Each red, green and blue current output should have a load resistor connected to AVDD. The resistors are typically 75 and should be kept in the 72 to 85 range. The outputs should drive a high impedance load such as a voltage follower. OUTPUT LEVEL SHIFTING CIRCUIT The SPT5230 voltage output will swing from +3.0 V to +4.99 V for VCS2 = 2.1 V as shown in table I. If level shifting of the output is desired, Fairchild recommends use of the circuit shown in figure 5. The desired -FS voltage is fed into the collector of the emitter to achieve the desired level shift. (Note the phase inversion that will occur due to the common emitter.) Choose any appropriate video op amp with adequate power supply head room. Table I - Binary Codes 1 LSB = 1.953 mV, VCS2 2.1 V Digital Input Analog A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Out (V)
(MSB) (LSB)
Step 0 1 2 3 . . . 1022 1023
0 0 0 0
0 0 0 0
0 0 0 0
1 1
1 1
1 1
0 0 0 0 . . . 1 1
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
1 1
1 1
1 1
1 1
0 0 1 1 . . . 1 1
0 1 0 1
3.000000 3.001953 3.003906 3.005859
0 4.996094 1 4.998047
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Figure 1 - Timing Diagram
N-Data th
ts
tpd 1/2 LSB
N-Output Level
1/2 LSB
Figure 2 - Output Voltage with All Digital Inputs = O versus VCS2
5.0
Figure 3 - Output Voltage (Vp-p) versus VCS2
2.5
Output Resistor = 75 TA = +25 C VREF1 = 3 V
4.5
Output Voltage (V) (-FS)
Output Resistor = 75 TA = +25 C Digital Inputs = All O VREF1 = 3 V
2.0
Output Voltage (Vp-p)
4.0
1.5
3.5
1.0
3.0
0.5
2.5 1.5 2.0 2.5 3.0 VCS2 (V) NOTE: For Digital Inputs = All 1, Output Voltage = +4.998047 V. 3.5 4.0 4.5
0.0 1.5 2.0 2.5 3.0 VCS2 (V) 3.5 4.0 4.5
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Figure 4 - Typical Interface Circuit
AVDD
1.2 k
BO (LSB)
AVDD 20 k
0.1 F
0.1 F
AVDD VREF2
CLKR
CLKG
CLKB
AVSS
B1
B5
B4
B3
B2
B6
6 k
36
32
28
37
33
29
38
34
30
39
35
31
27
VCS2
0.1 F
40 41 42 43 44 45 46 47 48 49 50 51 52
26 25 24 23 22 21
B7 B8 B9 (MSB) AVSS N/C GO (LSB) G1 G2 G3 G4 G5 G6 G7
AVDD 0.75 k 1.2 k
0.1 F
+5 V
VCS1 AVDD VREF1 AVSS BOUT AVSS GOUT AVSS ROUT AVSS AVDD AVDD
0.1 F
AVDD
75
AVDD
10 F
75
SPT5230
20 19 18 17 16 15 14
AVDD
75
12
10
13
11
4
8
3
7
2 R8
6
Figure 5 - Recommended Output Level Shifting Circuit
AVD
D
1 R9 (MSB)
5 R5
9
R6
R2
G9 (MSB)
R7
R3
N/C
R4
RO (LSB)
R1
G8
AVD
D
75
75 10 DAC 1 of 3 + 10 Out 75 NOTE: All three DACs use the same circuit configuration. -FS
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PACKAGE OUTLINE
52-Lead QFP
A B
39 27
SYMBOL A B C D E F G H I
INCHES MIN MAX 0.507 0.386 0.507 0.386 0.070 0.008 0.004 0.023 0.523 0.394 0.523 0.394 0.090 0.025 typ 0.016 0.062 typ 0.008 0.039
MILLIMETERS MIN MAX 13.0 9.9 13.0 9.9 1.80 0.2 1.6 typ 0.1 0.6 0.2 1.0 13.4 10.1 13.4 10.1 2.30 0.65 typ 0.4
40
26
C
D
52
14
J
H
1 13
J I
E
F
G
SPT5230
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PIN ASSIGNMENTS
BO (LSB) AVDD VREF2 38 39 CLKG 35 CLKR 36 CLKB AVSS 37
PIN FUNCTIONS
Name ROUT
B4 B3 B2 B6 B1 32 B5
Function Red Analog Current Output Green Analog Current Output Blue Analog Current Output Red Data Inputs Green Data Inputs Blue Data Inputs Red Clock Input Green Clock Input Blue Clock Input Voltage Reference Input 1 (A 0.1 F ceramic capacitor should be used.) Voltage Reference Input 2 (A 0.1 F ceramic capacitor should be used.) Control Voltage Decoupling (A 0.1 F ceramic capacitor should be used.) Full-Scale Adjust Control Voltage (A 0.1 F ceramic capacitor should be used.) Analog Ground Analog Power Supply Voltage No Connection
GOUT BOUT R0-R9
26 25 24 23 22 21 B7 B8 B9 (MSB) AVSS N/C GO (LSB) G1 G2 G3 G4 G5 G6 G7
33
29
34
30
31
27
28
VCS2 VCS1 AVDD VREF1 AVSS BOUT AVSS GOUT AVSS ROUT AVSS AVDD AVDD
40 41 42 43 44 45 46 47 48 49 50 51 52
G0-G9 B0-B9 CLKR CLKG CLKB VREF1 VREF2 VCS1 VCS2 AVSS AVDD N/C
QFP
20 19 18 17 16 15 14
1 1 10
13
12
3 R7
7
2 R8
6
ORDERING INFORMATION
PART NUMBER SPT5230SCT TEMPERATURE RANGE 0 to +70 C PACKAGE 52L QFP
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
www.fairchildsemi.com
1 R9 (MSB)
5 R5
9
4 R6
8 R2
RO (LSB)
G9 (MSB)
N/C
R3
R4
G8
R1
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
(c) Copyright 2002 Fairchild Semiconductor Corporation
SPT5230
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5/1/00

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